[ab9ca@class3 work]$ fm_shell

                            Formality (R)
                Version F-2011.09-SP2 -- Nov 22, 2011
              Copyright (c) 1988-2014 by Synopsys, Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys, Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

  ** Highlights of Formality 2011.09 **
   - Faster runtime and ease of use enhancements for UPF designs
   - Improved GUI usability and response for large designs
   - New, easy to use flow for ECO verification

   * Please refer to the Formality Release Notes for details and additional enhancements


Build: SP2
Hostname: class3.ee.Virginia.EDU (amd64)
Current time: Tue Apr 15 01:01:33 2014

Loading db file '/app/synopsys/formality/F-2011.12/libraries/syn/gtech.db'
fm_shell (setup)> source ../
./       ../      ref/     scripts/ source/  work/    
fm_shell (setup)> source ../
./       ../      ref/     scripts/ source/  work/    
fm_shell (setup)> source ../scripts/
./                     ../                    .fm_pre_script.tcl.swp fm_pre_script.tcl      
fm_shell (setup)> source ../scripts/fm_pre_script.tcl 
SVF set to '../source/default.svf'.
Loading db file '/net/humpback.ece.virginia.edu/scratch2/ab9ca/simulation/Synopsys/SynthMMUs/DMMU/formality/pre_lay/ref/models/saed32rvt_tt1p05v25c.db'
Current container set to 'r'
Loading verilog file '/net/humpback.ece.virginia.edu/scratch2/ab9ca/simulation/Synopsys/SynthMMUs/DMMU/formality/pre_lay/source/or1200_dmmu_tlb.v'
Loading include file '/net/humpback.ece.virginia.edu/scratch2/ab9ca/simulation/Synopsys/SynthMMUs/DMMU/formality/pre_lay/source/or1200_defines.v'
Loading include file '/net/humpback.ece.virginia.edu/scratch2/ab9ca/simulation/Synopsys/SynthMMUs/DMMU/formality/pre_lay/source/SRAM64x14.v'
Loading include file '/net/humpback.ece.virginia.edu/scratch2/ab9ca/simulation/Synopsys/SynthMMUs/DMMU/formality/pre_lay/source/SRAM64x24.v'
Warning: You are redefining a macro 'wordLength'.  (File: /net/humpback.ece.virginia.edu/scratch2/ab9ca/simulation/Synopsys/SynthMMUs/DMMU/formality/pre_lay/source/SRAM64x24.v Line: 18)  (FMR_VLOG-026)
Loading verilog file '/net/humpback.ece.virginia.edu/scratch2/ab9ca/simulation/Synopsys/SynthMMUs/DMMU/formality/pre_lay/source/or1200_dmmu_top.v'
Loading include file '/net/humpback.ece.virginia.edu/scratch2/ab9ca/simulation/Synopsys/SynthMMUs/DMMU/formality/pre_lay/source/or1200_defines.v'
Setting top design to 'r:/WORK/or1200_dmmu_top'
Status:   Elaborating design or1200_dmmu_top   ...  
Status:   Elaborating design or1200_dmmu_tlb   ...  
Status:   Elaborating design SRAM64x14   ...  
Status:   Elaborating design SRAM64x24   ...  
Status:  Implementing inferred operators...

************ Library Checking Summary ************
Warning:  18 unlinked power cell(s) with unread pg pins.
Warning:  17 unlinked power cell(s) with no retention ff or latch.
Warning:  1 unlinked power cell(s) with unread save/restore retention signals.
Warning:  68 unlinked power cell(s) with no power down function on an ff or latch.
        Use 'report_libraries -defects all' for more details.
**************************************************

Top design successfully set to 'r:/WORK/or1200_dmmu_top'
Reference design set to 'r:/WORK/or1200_dmmu_top'
Loading db file '/net/humpback.ece.virginia.edu/scratch2/ab9ca/simulation/Synopsys/SynthMMUs/DMMU/formality/pre_lay/ref/models/saed32rvt_tt1p05v25c.db'
Current container set to 'i'
Loading verilog file '/net/humpback.ece.virginia.edu/scratch2/ab9ca/simulation/Synopsys/SynthMMUs/DMMU/formality/pre_lay/source/dc_out_v/or1200_dmmu_top.v'
Setting top design to 'i:/WORK/or1200_dmmu_top_1'
Status:  Implementing inferred operators...

************ Library Checking Summary ************
Warning:  18 unlinked power cell(s) with unread pg pins.
Warning:  17 unlinked power cell(s) with no retention ff or latch.
Warning:  1 unlinked power cell(s) with unread save/restore retention signals.
Warning:  68 unlinked power cell(s) with no power down function on an ff or latch.
        Use 'report_libraries -defects all' for more details.
**************************************************

Top design successfully set to 'i:/WORK/or1200_dmmu_top_1'
Implementation design set to 'i:/WORK/or1200_dmmu_top_1'
Set 'r:/WORK/or1200_dmmu_top/clk' to constant 0
Set 'r:/WORK/or1200_dmmu_top/rst' to constant 0
Set 'i:/WORK/or1200_dmmu_top_1/clk' to constant 0
Set 'i:/WORK/or1200_dmmu_top_1/rst' to constant 0
Reference design is 'r:/WORK/or1200_dmmu_top'
Implementation design is 'i:/WORK/or1200_dmmu_top_1'
Status:  Checking designs...
    Warning: Design r:/WORK/SRAM64x14 is a black box and there are cells referencing it (FM-160)
    Warning: Design r:/WORK/SRAM64x24 is a black box and there are cells referencing it (FM-160)
    Warning: Design i:/WORK/SRAM64x14 is a black box and there are cells referencing it (FM-160)
    Warning: Design i:/WORK/SRAM64x24 is a black box and there are cells referencing it (FM-160)
    Warning: 2 (2) black-box references found in reference (implementation) design; see formality.log for list (FM-182)
Status:  Building verification models...
    Info:  set fm_rename_ref_top_to_imp_top true.
Imp top is or1200_dmmu_top_1 ; Ref top is or1200_dmmu_top 
Status:  Processing Guide Commands...
Status:  Generating datapath components ...
Status:  Qualifying datapath components ...
Status:  Datapath qualification complete.

***************************** Guidance Summary *****************************
                                         Status
Command                 Accepted   Rejected  Unsupported  Unprocessed  Total
----------------------------------------------------------------------------
environment         :          3          0          0          0          3
mark                :          2          0          0          0          2
transformation
   map              :          1          0          0          0          1

SVF files read:
  ../source/default.svf

SVF files produced:
  formality_svf/
    svf.txt
****************************************************************************

Status:  Matching...
    
*********************************** Matching Results ***********************************    
 130 Compare points matched by name    
 0 Compare points matched by signature analysis    
 0 Compare points matched by topology    
 116 Matched primary inputs, black-box outputs    
 0(0) Unmatched reference(implementation) compare points    
 0(0) Unmatched reference(implementation) primary inputs, black-box outputs    
 19(0) Unmatched reference(implementation) unread points    
****************************************************************************************

Reference design is 'r:/WORK/or1200_dmmu_top_1'
Implementation design is 'i:/WORK/or1200_dmmu_top_1'
    
*********************************** Matching Results ***********************************    
 130 Compare points matched by name    
 0 Compare points matched by signature analysis    
 0 Compare points matched by topology    
 116 Matched primary inputs, black-box outputs    
 0(0) Unmatched reference(implementation) compare points    
 0(0) Unmatched reference(implementation) primary inputs, black-box outputs    
 19(0) Unmatched reference(implementation) unread points    
****************************************************************************************

Status:  Verifying...

********************************* Verification Results *********************************
Verification SUCCEEDED
----------------------
 Reference design: r:/WORK/or1200_dmmu_top_1
 Implementation design: i:/WORK/or1200_dmmu_top_1
 130 Passing compare points
----------------------------------------------------------------------------------------
Matched Compare Points     BBPin    Loop   BBNet     Cut    Port     DFF     LAT   TOTAL
----------------------------------------------------------------------------------------
Passing (equivalent)          58       0       0       0      71       1       0     130
Failing (not equivalent)       0       0       0       0       0       0       0       0
****************************************************************************************
Info:  Session being saved in minimal format.
Error: No session file generated. Reason : unknown. (FM-427)
0

